Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for over twenty years for interconnected high I/O (input/output) count and area array solder bumps on the silicone chips to the base rigid ceramic chip carriers, for example alumina carriers. The solder bump, typically a 95Pb/5Sn alloy provides the means of chip attachment to the ceramic chip carrier for subsequent usage and testing. For example, see U.S. Pat. No. 3,401,126 and 3,429,040 to Miller and assigned to the assignee of the present application, for a further discussion of the controlled collapse chip connection (C4) technique of face down bonding of semiconductor chips to a rigid ceramic carrier. Typically a malleable pad of metallic solder is formed on the semiconductor device contact site and solder joinable sites are formed on the conductors on the chip carrier.
The device carrier solder joinable sites are surrounded by non-solderable barriers so that when the solder on the semiconductor device contact sites melts, surface tension of the molten solder prevents collapse of the joints and thus holds the semiconductor device suspended above the carrier.
With the development of the integrated circuit semiconductor device technology, the size of individual active and passive elements have become very small, and the number of elements in the device has increased dramatically. This results in significantly larger device sizes with larger numbers of I/O terminals.
An advantage of solder joining a device to a substrate is that the I/O terminals can be distributed over substantially the entire top surface of the semiconductor device. This allows an efficient use of the entire surface, which is more commonly known as area bonding.
Usually, the integrated circuit semiconductor devices are mounted on supporting substrates made of materials with thermal coefficients of expansion that differ from the thermal coefficient of expansion of the material of the semiconductor device, e.g. silicon. Normally the device is formed of monocrystalline silicon with a thermal coefficient of expansion of 2.5.times.10.sup.-6 per .degree.C. and the substrate is formed of a ceramic material typically alumina with a thermal coefficient of expansion of 5.8.times.10.sup.-6 per .degree.C. In operation, the active and passive elements of the integrated semiconductor device inevitably generate heat resulting in temperature fluctuations in both the devices and the supporting substrate since the heat is conducted through the solder bonds. The devices and the substrate thus expand and contract in different amounts with temperature fluctuations, due to the different coefficients of expansion. This imposes stresses on the relatively rigid solder terminals.
The stress on the solder bonds during operation is directly proportional to: (1) the magnitude of the temperature fluctuations; (2) the distance of an individual bond from the neutral or central point (DNP); and, (3) the difference in the coefficients of the expansion of the material of the semiconductor device and the substrate, and inversely proportional to the height of the solder bond, that is the spacing between the device and the support substrate. The seriousness of the situation is further compounded by the fact that as the solder terminals become smaller in diameter in order to accommodate the need for greater density, the overall height decreases.
There have been various suggestions to increase the fatigue life. For example, an improved solder interconnection structure with increased fatigue life is disclosed in U.S. Pat. No. 4,604,644 to Beckham et al. and assigned to the assignee of the present application, disclosure of which is incorporated herein by reference. In particular, U.S. Pat. No. 4,604,644 discloses a structure for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections where each solder connection is joined to a solder wettable pad on the device and a corresponding solder wettable pad on the support substrate. Dielectric organic material is disposed between the peripheral area of the device and the facing area of the substrate, which material surrounds at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of dielectric organic material.
More recently, further improved solder interconnection structures with even greater fatigue life have been disclosed in U.S. Pat. No. 4,999,699 and 5,089,440 to Christie et al. and assigned to the assignee of the present application, disclosures of which are incorporated herein by reference. In particular, the solder interconnection structure of these patents includes filling the gap between the carrier substrate and semiconductor device with a composition obtained from curing a curable composition containing a binder which is a cycloaliphatic polyepoxide and/or a cyanate ester or prepolymer thereof and a filler.
Moreover, solder interconnection between an organic substrate and semiconductor divided has been disclosed in U.S. Pat. No. 5,121,190 to Hsiao et al., and assigned to the assignee of the present application, disclosure of which is incorporated herein by reference. In particular, prior to the invention disclosed in U.S. Pat. No. 5,121,190, the attachment of a semiconductor device to organic substrates employing a C4 type connection had not been suggested. This was probably due to the fact that organic substrates present significant additional problems not experienced with employing ceramic substrates. For example, the differences in the coefficients of thermal expansion of the material of the semiconductor device, e.g. silicon and organic substrates greatly exceed that experienced with ceramic substrates. In fact, coefficient of thermal expansion mismatch is so great that attempts to attach the device to an organic substrate result in destroying any solder bond. Also, due to the flexible nature of organic substrates, including those that are fiber reinforced, these substrates tend to warp or bend during processing and temperature fluctuations. This greatly magnifies the problems associated with the destructive stress forces that would be placed upon any solder joint between the substrate and semiconductor device.
The invention of U.S. Pat. No. 5,121,190 made it possible to form a connection between an integrated semiconductor device and an organic substrate. This is accomplished by filling the gap between the carrier substrate and the semiconductor device with a composition obtained from curing a curable composition containing a thermo-setting binder and a filler. The binder employed typically has a viscosity at normal room temperatures (25.degree. C.) of no greater than about 1,000 centipoise. The filler typically has a maximum particle size of 50 microns.
Although, the above more recent techniques have been quite successful, there still remains room for alternative methods and/or improvements in increasing the fatigue life of the interconnections.